<meta http-equiv="refresh" content="0; URL=noscript.html"> METU | Course Syllabus

Course Learning Outcomes

Course Objective 1: Students will be able to have basic understanding of integrated circuit technology and basic fabrication steps of a CMOS process

Student Learning Outcomes

1.1 Understand basic process steps of a CMOS technology

1.2 Identify various regions of a CMOS process on the cross-sectional view

1.3 Understand mask making process and layout procedure

1.4 Understand parasitic devices and their effects

Course Objective 2: Students will be able to use an industrial commercial circuit simulation and design tool

Student Learning Outcomes

2.1 Understand the basic organization of the industrial commercial design tool

2.2 Learn to create schematics

2.3 Learn to perform simulations and plot data

2.4 Create layout of a circuit and perform various design verification procedures, like Design Rule Checks (DRC) and Layout versus Schematic (LVS) checks

Course Objective 3: Students will be able to understand basic electrical properties of MOS circuits

Student Learning Outcomes

3.1 Understand basic electrical characteristics of MOS transistors

3.2 Understand different use of MOS transistors

3.3 Understand the risk of latch-up due to parasitic BJT transistors in CMOS and ways to avoid latch-up

Course Objective 4: Students will be able design logic gates and create layouts of them

Student Learning Outcomes

4.1 Understand mask layers

4.2 Learn to create stick diagrams

4.3 Understand scalable CMOS design rules

4.4 Understand symbolic and stick diagrams

4.5 Learn Euler path approach for obtaining an efficient layout

Course Objective 5: Students will be understand parasitic effects

Student Learning Outcomes

5.1 Understand sheet resistance of metals

5.2 Understand capacitive effects

5.3 Understand the concept of propagation delays

Course Objective 6: Students will be able create hierarchical designs

Student Learning Outcomes

6.1 Learn to create hierarchical schematics

6.2 Learn to create hierarchical layouts

6.3 Understand the importance of hierarchical design

Course Objective 7: Students will be able design computational elements

Student Learning Outcomes

7.1 Learn to understand the difference between the logic design and VLSI design

7.2 Learn to implement data path operators efficiently

7.3 Learn the importance of regular designs

Course Objective 8: Students will be able design memory elements and design accurate clock distribution networks

Student Learning Outcomes

8.1 Understand elements with memory

8.2 Perform standard simulations on memory circuits

8.3 Understand the importance of accurate clock distribution

8.4 Learn ways to avoid race conditions.

Course Objective 9: Students will be able to create basic digital circuits with HDL

Student Learning Outcomes

9.1 Learn basic HDL language structure

9.2 Create basic digital cells with HDL language

9.3 Learn to syntheses from HDL