This course explores the design of cryptographic processors, covering hardware architectures for classical algorithms (AES, ECC) and post-quantum standards (Kyber, Dilithium, Falcon). Students will analyze speed/power/area (SPA) tradeoffs, implement side-channel-resistant designs, and optimize cryptographic cores (FPGA/ASIC) for both classical and post-quantum workloads, emphasizing real-world constraints like throughput and energy efficiency.