By completing this course, students will be able to (1) design efficient cryptographic processors for classical (AES/ECC) and post-quantum (Kyber/Dilithium) algorithms, (2) optimize hardware for SPA tradeoffs (speed/power/area), (3) implement side-channel and fault-attack countermeasures, and (4) benchmark designs using FPGA/ASIC toolchains for real-world constraints.